In order to exactly determine the performance of digital circuits, it is required to test them for different frequencies and duty cycles. The existing methods for testing digital circuits offer either frequency testing or duty cycle testing, but do not test for combinations of these parameters. Also, the conventional testers are generally external to the chip. The tester applies different frequencies to the circuit through the IO pads. The frequency limitation of the IO pads limits the frequency being fed into the circuit. The manual operations involved in the testing process further increase the testing time of the circuit. Owing to these limitations, designers have to rely on simulation results, which inherently differ from the behavior on the actual silicon.
U.S. Pat. No. 5,815,016 and U.S. Pat. No. 5,920,216 describe different approaches to generating a variable clock using voltage controlled programmable delays and synchronized clock frequencies or phases. However, these approaches do not provide any mechanism to determine maximum operational clock frequency.
U.S. Pat. No. 6,081,143 and U.S. Pat. No. 6,272,439 describe frequency monitors that compare two frequencies and accordingly either align the phase of a PLL or select/reject the input signals. However, they do not compute the maximum operating frequency and also do not provide any mechanism to characterize both frequency and duty cycle.
Thus, there is a need to develop a system that overcomes the above drawbacks.
Also, there is a need to develop a system that can provide both frequency and duty cycle characterization.